In many present day wireless communication applications, a digital synthesizer is used and often implemented by way of a digital phase locked loop (DPLL) that is used to control a digitally controlled oscillator (DCO) to generate (often referred to as ‘synthesize’) an output radio frequency (local oscillator) signal. Such digital synthesizers provide the benefit of simplifying the integration of the synthesizer circuitry within large scale integrated digital circuit devices, as compared with equivalent analogue synthesizers, thereby reducing size, cost, power consumption and design complexity. Furthermore, DPLLs intrinsically present lower phase noise than their analogue counterparts.
All-digital phase locked loops (ADPLLs) can be used as a frequency synthesizer in radio frequency circuits to create a stable local oscillator for transmitters or receivers, due to their low power consumption and high integration level. They can also be used to generate the frequency-modulated continuous wave (FMCW) waveforms required by a radar transmitter.
Modern FMCW radar systems require fast modulation ramps (with ramp-up times from 10 us to 100 us), but only process radar signals during ramp-up periods. Setting the ADPLL bandwidth is a delicate trade-off between good phase-noise (thus, low bandwidth) and high linearity of the FMCW ramps (thus, high bandwidth), and so the optimum bandwidth window is very narrow. In applications such as automotive radar systems, phase noise introduced into the output frequency signal by the synthesizer is a critical design factor.
As the DCO gain varies with frequency, say due to physical device behaviour, it also varies during the ramp modulation. This also causes the PLL bandwidth to vary, which may depart from the optimum bandwidth.
U.S. Pat. No. 7,466,207 B2 describes a way of measuring a value of a frequency gain (KDCO) of a DCO in an ADPLL by using the loop itself, for a given frequency, and adapting the kdco_est. However, the algorithm in U.S. Pat. No. 7,466,207 B2 takes a long time to converge, and is therefore only practically useful for fixed frequency scenarios and, in effect, unusable for systems that employ a wide range of frequencies.
Accordingly, for such applications, it is important to maintain a very tight control on the ADPLL bandwidth, even during wide-frequency FMCW modulation ramps.